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AX99100

AX99100

The AX99100 is a single chip solution that fully integrates PCIe 2.0 Gen 1 endpoint controller and SerDes with a variety of peripherals such as four High Speed Serial Ports, one Parallel Port, I²C Master, High Speed SPI, Local Bus (ISALike) , and GPIOs. It consists of four main configurations such as 4S (PCIe to Quad Serial), 2S+1P (PCIe to Dual Serial and Single Parallel), 2S+SPI (PCIe to Dual Serial and SPI), and LB (PCIe to Local Bus/ISALike) for different kinds of applications. The AX99100, in 68pin QFN, are available with RoHS compliant package and supports commercial grade operating temperature range from 0 to 70°C and industrial grade from 40 to 85°C. PCI Express Singlelane (X1) PCI Express Endpoint Controller with PHY integrated Compliant with PCI Express 2.0 Gen
SPB 180x1-1610

SPB 180x1-1610

Keilriemenscheibe SPB 180, 1-rillig für Taperlock 1610 1 -rillige Keilriemenscheibe SPB 180x1-1610 für Taperlockbuchse 1610Anzahl Rillen: 1 Wirkdurchmesser dp: 180 mmAussendurchmesser de: 187 mmNabendurchmesser Dm: 90 mmDI: 132 mmKranzbreite F: 25 mmGesamtbreite L: 25 mmScheibentyp: Vollscheibe Werkstoff: Grauguss EN-GJL-200 (G20 - UNI 5007) Zolltarifnummer: 84835020 Gewicht: 3,2 kgBenötigte Taperbuchse: 1610 Anzahl Rillen: 1 Wirkdurchmesser dp: 180 mm Aussendurchmesser de: 187 mm Nabendurchmesser Dm: 90 mm DI: 132 mm Kranzbreite F: 25 mm Gesamtbreite L: 25 mm Scheibentyp: Vollscheibe Zolltarifnummer: 84835020 Gewicht: 3,2 kg Benötigte Taperbuchse: 1610
Stiller

Stiller

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GS2971AIBE3

GS2971AIBE3

The GS2971A is a multirate SDI integrated Receiver which includes complete SMPTE processing, as per SMPTE 425M, 292M and SMPTE 259MC. The SMPTE processing features can be bypassed to support signals with other coding schemes. The GS2971A integrates Gennum's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals. The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. A serial digital loopthrough output is provided, which can be configured to output either reclocked or nonreclocked serial digital data. The serial digital output can be connected to an external cable driver. The device operates in one of four basic modes SMPTE mode, DVBASI mode, DataThrough mode or Standby mode.
AX11015

AX11015

Microcontrôleur à puce unique avec TCP/IP et 10/100M Fast Ethernet MAC/PHY (Caractéristiques 512K Flash, EMI, Local Bus, MII, 32GPIOs, LQFP128)The AX11015, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a SystemonChip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With builtin network protocol stack, the AX11015 provides very cost effective networking solution to enable simple, easy and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring and remote management. In addition to standalone application, the AX11015
BG96

BG96

BG96 est une série de LTE Cat.M1/Cat.NB1/EGPRS+ GNSS BG96 is a series of LTE Cat.M1/Cat.NB1/EGPRS module offering a maximum data rate of 375kbps downlink and uplink. It features ultra-low power consumption, and provides pin-to-pin compatibility with Quectel LTE module EG91/EG95, Cat.NB1 (NB-IoT) module BC95, UMTS/HSPA module UG95/UG96 and GSM/GPRS module M95. With a cost-effective SMT form factor of 22.5mm × 26.5mm × 2.3mm and high integration level, BG96 enables integrators and developers to easily design their applications and take advantage from the module’s low power consumption and mechanical intensity. Its advanced LGA package allows fully automated manufacturing for high-volume applications. Fast time-to-market:Reference designs, evaluation tools and timely technical support minimize design-in time